16th International Conference on Real-Time and Network Systems (RTNS 2008),
Rennes, France, 2008-10-18.
Attacking the Sources of Unpredictability in the Instruction Cache Behavior
By Enrico Mezzetti, Niklas Holsti, Antoine Colin, Guillem Bernat,
and Tullio Vardanega.
The use of cache memories challenges the design and
verification of high-integrity systems by making WCET analysis and
measurement, the central input to schedulability analysis, considerably
more laborious and less robust. In this paper we identify the sources of
instruction cache -related variability and gage them with ad-hoc
experiments. In that light, we perform a critical review of
state-of-the-art approaches to coping with and reducing the
unpredictability of cache behavior. Finally we single out practices and
recommendations that we deem best fit to attack the sources of
unpredictability and discuss their applicability to a real processor for
use in European space industry.
Paper (pdf, RTNS'08 site).